| (Times and speeds quoted are typical, but do not | | | | except the final test, maybe count=0, when the |
| refer to any specific hardware, merely give an | | | | branch occurs.Now consider the speed gains to be |
| illustration of the principles involved.)Now we | | | | made with disks. Being a mechanical device, a disk |
| introduce a 'high speed' memory with a cycle time of, | | | | works in milliseconds, so loading a program or data |
| say 250 nanoseconds between the CPU and the core | | | | from disk is extremely slow in comparison, even to |
| memory. When we request the first instruction, at | | | | core memory - 1000 times faster! Also there is a |
| location 100, the cache memory requests addresses | | | | seek time and latency to be considered. (This is |
| 100,101,102 and 103 from the core memory all at the | | | | covered in another article on disks.)You may have |
| same time, and retains them 'in cache'. Instruction 100 | | | | heard the term DMA in relation to PCs. This refers to |
| is passed to the CPU for processing, and the next | | | | Direct Memory Access. Which means that data can |
| request, for 101, is filled from the cache. Similarly 102 | | | | be transferred to or from the disk directly to |
| and 103 are handled at the much increased repeat | | | | memory, without passing through any other |
| speed of 250ns. In the meantime the cache memory | | | | component. In a mainframe computer, typically the I |
| has requested the next 4 addresses, 104 to 107. This | | | | O or Input/Output processor has direct access to |
| continues until the predicted 'next location' is incorrect. | | | | memory, using data placed there by the Processor. |
| The process is then repeated to reload the cache | | | | This path is also boosted by using cache memory.In |
| with data for the new address range. A correctly | | | | the PC, the CPU chip now has built-in cache. Level 1, |
| predicted address, when the requested location is in | | | | or L1, cache is the primary cache in the CPU which is |
| cache is known as a cache 'hit'.If the main memory is | | | | SRAM or Static RAM. This is high speed (and more |
| not core, but a slower chip memory, the gains are | | | | expensive) memory compared to DRAM or Dynamic |
| not as great, but still an improvement. Expensive high | | | | RAM, which is used for system memory. L2 cache, |
| speed memory is only required for a fraction of the | | | | also SRAM, may be incorporated in the CPU or |
| capacity of the cheaper main memory. Also | | | | externally on the Motherboard. It has a larger |
| programmers can design programs to suit the cache | | | | capacity than L1 cache.Tony is an experienced |
| operation, for instance by making a branch instruction | | | | computer engineer. |
| in a loop take the next instruction for all cases | | | | |